This invention relates to a capacitor electrode of a capacitor in a semiconductor device, and more specifically to methods for fabricating a multiple tubular like shaped capacitor electrode.
Dynamic Random Access Memory (DRAM) semiconductor devices are commodity products widely used in many electronic applications. A conventional DRAM cell capacitor includes a storage node and a plate node with a thin dielectric disposed there between. An access transistor whose gate is connected to a word line, is connected in series between one of the capacitor electrodes and a bit line. Data is stored as a presence or absence of charge on the storage node. The access transistor either isolates the data stored on the storage node when in a non-conducting state or allows the reading or writing of the data by coupling the capacitor storage node to a bit line when in a conducting state.
As integrated circuit technology is continually driven toward smaller device sizes, the area in which the DRAM cell occupies should be reduced to achieve a higher density. The capacitance of the DRAM cell is proportional to a capacitor electrode surface area and an adequate capacitance of the cell capacitor must be maintained for maintaining a proper charge storage retention period, which is a maximum time that the charge is maintained on the storage node before a refresh operation is required.
Many techniques for increasing the effective capacitance of a DRAM cell have been proposed. Many of these techniques involve fabricating a three dimensional capacitor electrode structure in order to maximize an effective electrode surface area in a given two dimensional space. However many of these techniques involve expensive and time consuming process steps.
Recently, new technologies have been developed to increase the effective electrode surface area by modifying the surface morphology of the capacitor electrode itself. For example, growing a hemispherical grain silicon (HSG) layer on a capacitor storage node will increase the effective electrode surface area, however it has several problems when using a design rule of less than approximately 0.21 microns. One such problem when using HSGs is twin-bit failure. Twin-bit failure occurs when there is insufficient area between adjacent storage nodes, such that the storage nodes become connected to each other through the HSGs.
Accordingly, there is a need for a capacitor electrode structure for very high density DRAM devices that achieves a large surface area while eliminating twin-bit failure. In addition, a method for fabricating a capacitor electrode structure is needed which minimizes process complexity in order to save on processing costs and processing time in forming a three dimensional capacitor electrode structure which may achieve a maximum amount of surface area in a minimum allowable area.